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1. general description the 74abt821 high-performance bicmos device combines low static and dynamic power dissipation with high sp eed and high output drive. the 74abt821 bus interface register is design ed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. the 74abt821 is a buffered 10-bit wide version of the 74abt374a. the 74abt821 is a 10-bit, edge-triggered register coupled to ten 3-state output buffers. the device is controlled by the clock (cp) and output enable ( oe ) control gates. the register is fully edge triggered. the stat e of each d input, one set-up time before the low-to-high clock transition is transferred to the corresponding output q of the flip-flop. the 3-state output buffers are designed to drive heavily loaded 3-state buses, mos memories, or mos microprocessors. the active low output enable ( oe ) controls all ten 3-state buffers independent of the register operation. when oe is low, the data in the register appears at the outputs. when oe is high, the outputs are in high-imp edance off-state, which means they will neither drive nor load the bus. 2. features and benefits ? high-speed parallel registers with positi ve-edge triggered d-type flip-flops ? ideal where high speed, light loading, or increased fan-in are required with mos microprocessors ? output capability: +64 ma and ? 32 ma ? power-on 3-state ? power-on reset ? latch-up protection exceeds 500 ma per jesd78b class ii level a ? esd protection: ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v 74abt821 10-bit d-type flip-flop; posit ive-edge trigger; 3-state rev. 04 ? 26 march 2010 product data sheet
74abt821_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 26 march 2010 2 of 16 nxp semiconductors 74abt821 10-bit d-type flip-flop; positive-edge trigger; 3-state 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74abt821d ? 40 c to +85 c so24 plastic small outline package; 24 leads; body width 7.5 mm sot137-1 74ABT821DB ? 40 c to +85 c ssop24 plastic shrink small outline package; 24 leads; body width 5.3 mm sot340-1 74abt821pw ? 40 c to +85 c tssop24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 fig 1. logic symbol fig 2. iec logic symbol 001aac73 4 d0 13 1 cp oe d1 d2 d3 d4 d5 d6 d7 d8 d9 q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 23 22 21 20 19 18 17 16 15 14 234567891011 1 2d 1 en 13 c2 2 23 322 421 520 619 718 817 916 10 15 11 14 001aac735 fig 3. logic diagram 001aac736 d0 q0 d 2 23 1 13 cp cp oe q d1 q1 d 3 22 cp q d2 q2 d 4 21 cp q d3 q3 d 5 20 cp q d4 q4 d 6 19 cp q d5 q5 d 7 18 cp q d6 q6 d 8 17 cp q d7 q7 d 9 16 cp q d8 q8 d 10 15 cp q d9 q9 d 11 14 cp q
74abt821_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 26 march 2010 3 of 16 nxp semiconductors 74abt821 10-bit d-type flip-flop; positive-edge trigger; 3-state 5. pinning information 5.1 pinning 5.2 pin description fig 4. pin configuration 74abt821 oe v cc d0 q0 d1 q1 d2 q2 d3 q3 d4 q4 d5 q5 d6 q6 d7 q7 d8 q8 d9 q9 gnd cp 001aac733 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 table 2. pin description symbol pin description oe 1 output enable input (active low) d0 to d9 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 data input gnd 12 ground (0 v) cp 13 clock pulse input (active rising edge) q0 to q9 23, 22, 21, 20, 19, 18, 17, 16, 15, 14 data output v cc 24 supply voltage
74abt821_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 26 march 2010 4 of 16 nxp semiconductors 74abt821 10-bit d-type flip-flop; positive-edge trigger; 3-state 6. functional description 6.1 function table [1] h = high voltage level; h = high voltage level one set-up time pr ior to the low-to-high clock transition; l = low voltage level; i = low voltage level one set-up time prior to the low-to-high clock transition; nc = no change; x = don?t care; z = high-impedance off-state; = low-to-high clock transition. table 3. function table [1] input internal register output operating mode oe cp d0 to d9 q0 to q9 l l l l load and read register l h h h l nc x nc nc hold h nc x nc z disable outputs h dn dn z
74abt821_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 26 march 2010 5 of 16 nxp semiconductors 74abt821 10-bit d-type flip-flop; positive-edge trigger; 3-state 7. limiting values [1] the input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] the performance capability of a high-perfo rmance integrated circuit in conjunction with its thermal environment can create j unction temperatures which are detrimental to reli ability. the maximum junction temperature of this integrated circuit should not excee d 150 c. 8. recommended operating conditions table 4. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +7.0 v v i input voltage [1] ? 1.2 +7.0 v v o output voltage output in off-state or high-state [1] ? 0.5 +5.5 v i ik input clamping current v i < 0 v ? 18 - ma i ok output clamping current v o < 0 v ? 50 - ma i o output current output in low-state - 128 ma t j junction temperature [2] - 150 c t stg storage temperature ? 65 +150 c table 5. recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage 4.5 - 5.5 v v i input voltage 0 - v cc v v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v i oh high-level output current ? 32 - - ma i ol low-level output current - - 64 ma t/ v input transition rise and fall rate 0 - 5 ns/v t amb ambient temperature in free air ? 40 - +85 c
74abt821_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 26 march 2010 6 of 16 nxp semiconductors 74abt821 10-bit d-type flip-flop; positive-edge trigger; 3-state 9. static characteristics [1] for valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. [2] this parameter is valid for any v cc between 0 v and 2.1 v with a transition time of up to 10 ms. for v cc = 2.1 v to v cc = 5 v 10 %, a transition time of up to 100 s is permitted. [3] not more than one output should be tested at a time, and the duration of the test should not exceed one second. [4] this is the increase in supply current for each input at 3.4 v. table 6. static characteristics symbol parameter conditions 25 c ? 40 c to +85 c unit min typ max min max v ik input clamping voltage v cc = 4.5 v; i ik = ? 18 ma ? 1.2 ? 0.9 - ? 1.2 - v v oh high-level output voltage v i = v il or v ih v cc = 4.5 v; i oh = ? 3 ma 2.5 2.9 - 2.5 - v v cc = 5.0 v; i oh = ? 3 ma 3.0 3.4 - 3.0 - v v cc = 4.5 v; i oh = ? 32 ma 2.0 2.4 - 2.0 - v v ol low-level output voltage v cc = 4.5 v; i ol = 64 ma; v i = v il or v ih - 0.42 0.55 - 0.55 v v ol(pu) power-up low-level output voltage v cc = 5.5 v; i o = 1 ma; v i = gnd or v cc [1] - 0.13 0.55 - 0.55 v i i input leakage current v cc = 5.5 v; v i = gnd or 5.5 v - 0.01 1.0 - 1.0 a i off power-off leakage current v cc = 0 v; v i or v o 4.5 v - 5.0 100 - 100 a i o(pu/pd) power-up/power-down output current v cc = 2.0 v; v o = 0.5 v; v i = gnd or v cc ; oe n high [2] - 5.0 50 - 50 a i oz off-state output current v cc = 5.5 v; v i = v il or v ih v o = 2.7 v - 5.0 50 - 50 a v o = 0.5 v - ? 5.0 ? 50 - ? 50 a i lo output leakage current high-state; v o = 5.5 v; v cc = 5.5 v; v i = gnd or v cc - 5.0 50 - 50 a i o output current v cc = 5.5 v; v o = 2.5 v [3] ? 180 ? 80 ? 50 ? 180 ? 50 ma i cc supply current v cc = 5.5 v; v i = gnd or v cc outputs high-state - 0.5 250 - 250 a outputs low-state - 25 38 - 38 ma outputs disabled - 0.5 250 - 250 a i cc additional supply current per input pin; v cc = 5.5 v; one input at 3.4 v; other inputs at v cc or gnd [4] - 0.5 1.5 - 1.5 ma c i input capacitance v i = 0 v or v cc - 4 - - - pf c o output capacitance outputs disabled; v o = 0 v or v cc - 7 - - - pf
74abt821_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 26 march 2010 7 of 16 nxp semiconductors 74abt821 10-bit d-type flip-flop; positive-edge trigger; 3-state 10. dynamic characteristics 11. waveforms table 7. dynamic characteristics gnd = 0 v; for test circuit, see figure 8 . symbol parameter conditions 25 c; v cc = 5.0 v ? 40 c to +70 c; v cc = 5.0 v 0.5 v unit min typ max min max t plh low to high propagation delay cp to qn; see figure 5 2.1 4.1 5.6 2.1 6.2 ns t phl high to low propagation delay cp to qn; see figure 5 2.8 4.6 6.2 2.8 6.7 ns t pzh off-state to high propagation delay oe n to qn; see figure 6 1.0 3.0 4.5 1.0 5.3 ns t pzl off-state to low propagation delay oe n to qn; see figure 6 2.2 4.1 5.6 2.2 6.3 ns t phz high to off-state propagation delay oe n to qn; see figure 6 2.7 4.7 6.2 2.7 6.7 ns t plz low to off-state propagation delay oe n to qn; see figure 6 2.3 4.6 6.1 2.3 6.5 ns t su(h) set-up time high dn to cp; see figure 7 2.1 0.5 - 2.1 - ns t su(l) set-up time low dn to cp; see figure 7 2.1 0.3 - 2.1 - ns t h(h) hold time high dn to cp; see figure 7 1.3 0 - 1.3 - ns t h(l) hold time low dn to cp; see figure 7 1.3 ? 0.3 - 1.3 - ns t wh pulse width high cp; see figure 5 2.9 1.8 - 2.9 - ns t wl pulse width low cp; see figure 5 3.8 2.8 - 3.8 - ns f max maximum frequency see figure 5 125 185 - 125 - mhz v m = 1.5 v v ol and v oh are typical voltage output levels that occur with the output load. fig 5. propagation delay clock input (cp) to output (qn), clock pulse (cp) width and maximum clock (cp) frequency 001aac44 5 cp input qn output t phl t plh t wh t wl 1 / f max v m v oh v i gnd v ol v m
74abt821_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 26 march 2010 8 of 16 nxp semiconductors 74abt821 10-bit d-type flip-flop; positive-edge trigger; 3-state v m = 1.5 v. v ol and v oh are typical voltage output levels that occur with the output load. fig 6. 3-state output (qn) enable and disable times v m = 1.5 v the shaded areas indicate when the input is permitted to change for predictable output performance. fig 7. set-up and hold times da ta input (dn) to clock (cp) 001aal29 9 t plz t phz outputs disabled outputs enabled v oh ? 0.3 v v ol + 0.3 v outputs enabled output low-to-off off-to-low output high-to-off off-to-high oe input v i v ol v oh 3.5 v v m gnd gnd t pzl t pzh v m v m 001aac73 8 v m cp input v m v m v m v m v m t su(h) t h(h) t su(l) t h(l) dn input v l gnd v l gnd
74abt821_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 26 march 2010 9 of 16 nxp semiconductors 74abt821 10-bit d-type flip-flop; positive-edge trigger; 3-state a. input pulse definition b. test circuit test data and v ext levels are given in table 8 . r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to output impedance z o of the pulse generator. v ext = test voltage for switching times. fig 8. test circuit for measuring switching times 001aai29 8 v m v m t w t w 10 % 90 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % 90 % 10 % 10 % t f t r t r t f v ext v cc v i v o mna61 6 dut c l r t r l r l g table 8. test data input load v ext v i f i t w t r , t f c l r l t phl , t plh t pzh , t phz t pzl , t plz 3.0 v 1 mhz 500 ns 2.5 ns 50 pf 500 open open 7.0 v
74abt821_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 26 march 2010 10 of 16 nxp semiconductors 74abt821 10-bit d-type flip-flop; positive-edge trigger; 3-state 12. package outline fig 9. package outline sot137-1 (so24) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot137-1 x 12 24 w m a a 1 a 2 b p d h e l p q detail x e z c l v m a 13 (a ) 3 a y 0.25 075e05 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.61 0.60 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 e 1 0 5 10 mm scale s o24: plastic small outline package; 24 leads; body width 7.5 mm sot137 -1 99-12-27 03-02-19
74abt821_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 26 march 2010 11 of 16 nxp semiconductors 74abt821 10-bit d-type flip-flop; positive-edge trigger; 3-state fig 10. package outline sot340-1 (ssop24) unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 1.25 7.9 7.6 0.9 0.7 0.8 0.4 8 0 o o 0.13 0.1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.2 mm maximum per side are not included. 1.03 0.63 sot340-1 mo-150 99-12-27 03-02-19 x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 112 24 13 0.25 y pin 1 index 0 2.5 5 mm scale s sop24: plastic shrink small outline package; 24 leads; body width 5.3 mm sot340 -1 a max. 2
74abt821_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 26 march 2010 12 of 16 nxp semiconductors 74abt821 10-bit d-type flip-flop; positive-edge trigger; 3-state fig 11. package outline sot355-1 (tssop24) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 0.4 0.3 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot355-1 mo-153 99-12-27 03-02-19 0.25 0.5 0.2 w m b p z e 112 24 13 pin 1 index a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a d y 0 2.5 5 mm scale tssop24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355 -1 a max. 1.1
74abt821_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 26 march 2010 13 of 16 nxp semiconductors 74abt821 10-bit d-type flip-flop; positive-edge trigger; 3-state 13. abbreviations 14. revision history table 9. abbreviations acronym description bicmos bipolar complementary metal-oxide semiconductor dut device under test esd electrostatic discharge hbm human body model mm machine model table 10. revision history document id release date data sheet status change notice supersedes 74abt821_4 20100326 product data sheet - 74abt821_3 74abt821_3 20100225 product data sheet - 74abt821_2 modifications: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. ? dip 24 (sot222-1) package removed from section 3 ? ordering information ? and section 12 ? package outline ? . 74abt821_2 20050412 product specification - 74abt821 74abt821 19950906 product specification - -
74abt821_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 26 march 2010 14 of 16 nxp semiconductors 74abt821 10-bit d-type flip-flop; positive-edge trigger; 3-state 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qua lified for use in automotive applications. the product is not desi gned, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be ex pected to result in personal injury, death or severe property or environmental dam age. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer?s third party customer(s) (hereinafter both referred to as ?application?). it is customer?s sole responsibility to check whether the nxp semiconductors product is suitable and fit for the application planned. customer has to do all necessary testing for the application in order to avoid a default of the application and the product. nxp semiconducto rs does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objec tive specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74abt821_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 26 march 2010 15 of 16 nxp semiconductors 74abt821 10-bit d-type flip-flop; positive-edge trigger; 3-state 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74abt821 10-bit d-type flip-flop; positive-edge trigger; 3-state ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 26 march 2010 document identifier: 74abt821_4 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 functional description . . . . . . . . . . . . . . . . . . . 4 6.1 function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 recommended operating conditions. . . . . . . . 5 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 6 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 14 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 15.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 16 contact information. . . . . . . . . . . . . . . . . . . . . 15 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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